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lt c1605-1/ lt c1605-2 1 160512fa for more information www.linear.com/ltc1605-1 typical application features description single supply 16-bit, 100ksps, sampling adcs the lt c ? 1 605- 1/ ltc1605-2 are 100ksps , sampling 16- bit a / d converters that draw only 55mw (typical) from a single 5v supply . these easy-to-use devices include a sample-and-hold, precision reference , switched capacitor successive approximation a / d and trimmed internal clock . the ltc1605-1 s input range is 0v to 4v while the ltc1605-2 s input range is 4v. an external reference can be used if greater accuracy over temperature is needed.the adc has a microprocessor compatible , 16- bit or two byte parallel output port . a convert start input and a data ready signal ( busy ) ease connections to fifos , dsps and microprocessors. applications n sample rate: 100ksps n complete 16-bit solution on a single 5v supply n unipolar input range: 0v to 4v (ltc1605-1) n bipolar input range: 4v (ltc1605-2) n power dissipation: 55mw typ n signal-to-noise ratio: 86db typ n operates with internal or external reference n internal synchronized clock n 28-pin ssop package n industrial process control n multiplexed data acquisition systems n high speed data acquisition for pcs n digital signal processing l , ltc and lt are registered trademarks of linear technology corporation. ltc1605-1 low power, 100khz, 16-bit sampling adc on 5v supply 4k 4k 200 2.5v reference 20k 10k 16-bit sampling adc d15 to d0 33.2k 2.2f 2.5v2.5v 10f 0.1f 2.2f 0v to 4v input v in capref agnd1 14 2 agnd2 5 dgnd 14 control logic and timing byte cs r/ c 28 27 6 to 13 15 to 22 2625 24 23 digitalcontrol signals 1605-1/2 ta01 16-bitor 2 byte parallel bus 5v v dig v ana buffer 3 busy code 0 inl (lsbs) 65535 1605-1/2 ta02/g04 16384 32768 49152 2.01.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 typical inl curve downloaded from: http:///
lt c1605-1/ lt c1605-2 2 160512fa for more information www.linear.com/ltc1605-1 absolute maximum ratings v ana .......................................................................... 7v v dig to v ana ............................................................ 0. 3v v dig ........................................................................... 7v ground voltage difference dgnd , ag nd1 and ag nd2 ................................ 0. 3v analog inputs ( note 3 ) v in ..................................................................... 25v cap ............................. v ana + 0. 3v to ag nd2 C 0. 3v ref .................................... indefinite short to ag nd2 momentary short to v ana (notes 1, 2) 12 3 4 5 6 7 8 9 1011 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 v in agnd1 ref cap agnd2 d15 (msb) d14d13 d12 d11 d10 d9d8 dgnd v dig v ana busycs r/ c byted0 d1 d2 d3 d4 d5 d6 d7 g package 28-lead plastic ssop top view t jmax = 125c, ja = 95c/w exposed pad (pin #) is gnd, must be soldered to pcb t jmax = 125c, ja = 130c/w obsolete package pin configuration digital input voltage ( note 4 ) ......... v dgnd C 0. 3v to 10v digital output voltage ........ v dgnd C 0. 3v to v dig + 0. 3v power dissipation .............................................. 500mw operating ambient temperature range lt c1605 - 1c / lt c1605 - 2c ......................... 0c to 70c lt c1605 -1i / lt c1605 -2i ....................... C 40 c to 85c storage temperature range .................. C 65 c to 150c lead temperature ( soldering , 10 sec ) ................... 300 c downloaded from: http:/// 12 3 4 5 6 7 8 9 1011 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 v in agnd1 ref cap agnd2 d15 (msb) d14d13 d12 d11 d10 d9d8 dgnd v dig v ana busycs r/ c byted0 d1 d2 d3 d4 d5 d6 d7 n package 28-lead pdip top view
lt c1605-1/ lt c1605-2 3 160512fa for more information www.linear.com/ltc1605-1 converter characteristics analog input parameter conditions min typ max units resolution l 16 bits no missing codes l 15 bits transition noise 1 lsb rms integral linearity error (note 7) l 3 lsb zero error ext. reference = 2.5v (note 8) l 10 mv zero error drift 2 ppm/c full-scale error drift 7 ppm/c full-scale error ext. reference = 2.5v (notes 12, 13) l 0.50 % full-scale error drift ext. reference = 2.5v 2 ppm/c power supply sensitivity v ana = v dig = v dd v dd = 5v 5% (note 9) 8 lsb the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. with external reference (notes 5, 6). the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (note 9) 4.75v v ana 5.25v, 4.75v v dig 5.25v ltc1605-1 ltc1605-2 l l 0 to 4 4 v v c in analog input capacitance 10 pf r in analog input impedance 10 k lead free finish tape and reel part marking package description temperature range ltc1605-1cg#pbf ltc1605-1cg#trpbf ltc1605-1cg 28-lead plastic ssop 0c to 70c ltc1605-1ig#pbf ltc1605-1ig#trpbf ltc1605-1ig 28-lead plastic ssop C40c to 85c ltc1605-2cg#pbf ltc1605-2cg#trpbf ltc1605-2cg 28-lead plastic ssop 0c to 70c ltc1605-2ig#pbf ltc1605-2ig#trpbf ltc1605-2ig 28-lead plastic ssop C40c to 85c obsolete package ltc1605-1cn#pbf ltc1605-1cn#trpbf ltc1605-1cn 28-lead pdip 0c to 70c ltc1605-1in#pbf ltc1605-1in#trpbf ltc1605-1in 28-lead pdip C40c to 85c ltc1605-2cn#pbf ltc1605-2cn#trpbf ltc1605-2cn 28-lead pdip 0c to 70c ltc1605-2in#pbf ltc1605-2in#trpbf ltc1605-2in 28-lead pdip C40c to 85c consult factory for military grade parts. consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part markings, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ order information downloaded from: http:///
lt c1605-1/ lt c1605-2 4 160512fa for more information www.linear.com/ltc1605-1 internal reference characteristics digital inputs and digital outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v ih high level input voltage vdd = 5.25v l 2.4 v v il low level input voltage v dd = 4.75v l 0.8 v i in digital input current v in = 0v to v dd l 10 a c in digital input capacitance 5 pf v oh high level output voltage v dd = 4.75v i o = C10a 4.5 v i o = C200a l 4.0 v v ol low level output voltage v dd = 4.75v i o = 160a 0.05 v i o = 1.6ma l 0.10 0.4 v i oz hi-z output leakage d15 to d0 v out = 0v to v dd , cs high l 10 a c oz hi-z output capacitance d15 to d0 cs high (note 9) l 15 pf i source output source current v out = 0v C10 ma i sink output sink current v out = v dd 10 ma parameter conditions min typ max units v ref output voltage i out = 0 l 2.470 2.500 2.520 v v ref output tempco i out = 0 5 ppm/c internal reference source current 1 a external reference voltage for specified linearity (notes 9, 10) 2.30 2.50 2.70 v external reference current drain ext. reference = 2.5v (note 9) l 100 a cap output voltage i out = 0 2.50 v dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 5, 14) symbol parameter conditions min typ max units s/(n + d) signal-to-(noise + distortion) ratio 1khz input signal (note 14) 10khz input signal 20khz, C60db input signal 87 85 30 db db db thd total harmonic distortion 1khz input signal, first 5 harmonics 10khz input signal, first 5 harmonics C101 -92 db db peak harmonic or spurious noise 1khz input signal 10khz input signal C101 -92 db db full-power bandwidth (note 15) 275 khz aperture delay 40 ns aperture jitter sufficient to meet ac specs transient response full-scale step (note 9) 2 s overvoltage recovery (note 16) 150 ns downloaded from: http:///
lt c1605-1/ lt c1605-2 5 160512fa for more information www.linear.com/ltc1605-1 timing characteristics power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units f sample(max) maximum sampling frequency l 100 khz t conv conversion time l 8 s t acq acquisition time l 2 s t 1 convert pulse width (note 11) l 40 ns t 2 data valid delay after r/ c (note 9) l 8 s t 3 busy delay from r/ c c l = 50pf l 65 ns t 4 busy low 8 s t 5 busy delay after end of conversion 220 ns t 6 aperture delay 40 ns t 7 bus relinquish time l 10 35 83 ns t 8 busy delay after data valid l 50 200 ns t 9 previous data valid after r/ c 7.4 s t10 r/ c to cs setup time (notes 9, 10) 10 ns t11 time between conversions 10 s t12 bus access and byte delay (notes 9, 10) 10 83 ns symbol parameter conditions min typ max units v dd positive supply voltage (notes 9, 10) 4.75 5.25 v i dd positive supply current l 11 16 ma p dis power dissipation 55 80 mw note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with dgnd, agnd1 and agnd2 wired together (unless otherwise noted). note 3: when these pin voltages are taken below ground or above v ana = v dig = v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below ground or above v dd without latch-up.note 4: when these pin voltages are taken below ground, they will be clamped by internal diodes. this product can handle input currents of 90ma below ground without latchup. these pins are not clamped to v dd . note 5: v dd = 5v, f sample = 100khz, t r = t f = 5ns unless otherwise specified.note 6: linearity, offset and full-scale specifications apply for a v in input with respect to ground.note 7: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. the deviation is measured from the center of the quantization band. note 8: zero error for the lt c1605-1 is the voltage measured from 0.5lsb when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001. zero error for the lt c1605 -2 is the voltage measured from ? 0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111.note 9: guaranteed by design, not subject to test. note 10: recommended operating conditions. note 11: with cs low the falling r/ c edge starts a conversion. if r/ c returns high at a critical point during the conversion it can create small errors. for best results ensure that r/ c returns high within 3s after the start of the conversion.note 12: as measured with fixed resistors shown in figure 4. adjustable to zero with external potentiometer. note 13: full-scale error is the untrimmed deviation from ideal last code transition, divided by the full-scale range and includes the effect of offset error. note 14: all specifications in db are referred to a full-scale 4v input for the lt c1605-1 and to 4v input for the lt c1605-2. note 15: full-power bandwidth is defined as full-scale input frequency at which a signal-to-(noise + distortion) degrades to 60db or 10 bits of accuracy. note 16: recovers to specified performance after (20v) input overvoltage for the lt c1605-1 and 15v for the lt c1605-2. downloaded from: http:///
lt c1605-1/ lt c1605-2 6 160512fa for more information www.linear.com/ltc1605-1 typical performance characteristics typical inl curve typical dnl curve power supply feedthrough vs ripple frequency ltc1605-2 nonaveraged 4096-point fft plot sinad vs input frequency (ltc1605-2) total harmonic distortion vs input frequency (ltc1605-2) supply current vs supply voltage supply current vs temperature change in cap voltage vs load current supply voltage (v) 4.50 9.5 supply current (ma) 10.0 10.5 11.0 11.5 12.0 12.5 4.75 5.00 5.25 5.50 1605-1/2 g01 f sample = 100khz temperature (?c) ?50 10.0 power supply current (ma) 10.5 11.0 11.5 12.0 ?25 0 25 50 1605-1/2 g02 75 100 f sample = 100khz load current (ma) change in cap voltage (v) 0.040.02 0 C0.02 C0.04 C0.06 C0.08 C0.10 C60 C40 C20 0 1605-1/2 g03 C70 C80 C50 C30 C10 10 ltc1605-1 ltc1605-2 code 0 inl (lsbs) 65535 1605-1/2 ta02/g04 16384 32768 49152 2.01.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 code 0 dnl (lsb) 65535 1605-1/2 g05 16384 32768 49152 2.01.5 1.0 0.5 0 C0.5 C1.0 C1.5 C2.0 ripple frequency (hz) power supply feedthrough (db) C20 C30 C40 C50 C60 C70 C80 100 10k 100k 1m ltxxxx gxx 1k ltc1605-2 ltc1605-1 frequency (khz) 0 magnitude (db) 1605-1/2 g07/f11 5 10 15 20 25 30 35 40 45 50 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 C130 f sample = 100khz f in = 1khz sinad = 87dbthd = 101.1db snr = 87.2db input frequency (khz) 1 sinad (db) 9088 86 84 82 80 10 100 1605-1/2 g08 input frequency (khz) 1 total harmonic distortion (db) C70 C80 C90 C100 C110 10 100 1605-1/2 g09 downloaded from: http:///
lt c1605-1/ lt c1605-2 7 160512fa for more information www.linear.com/ltc1605-1 pin functions vin ( pin 1 ): analog input . connect through a 200 resistor to the analog input . full-scale input range is 0v to 4v for the ltc1605 -1 and 4v for the ltc1605-2 . agnd1 ( pin 2 ): analog ground . tie to analog ground plane . ref ( pin 3 ): 2. 5v reference output . bypass with 2.2f tantalum capacitor . can be driven with an external refer - ence . cap ( pin 4 ): reference buffer output . bypass with 2.2f tantalum capacitor.agnd2 ( pin 5 ): analog ground . tie to analog ground plane . d15 to d8 ( pins 6 to 13 ): three-state data outputs . hi-z state when cs is high or when r/ c is low. dgnd (pin 14): digital ground. d7 to d0 ( pins 15 to 22 ): three-state data outputs . hi-z state when cs is high or when r/ c is low. byte ( pin 23 ): byte select . with byte low , data will be output with pin 6 (d15) being the msb and pin 22 (d0) being the lsb . with byte high the upper eight bits and the lower eight bits will be switched . the msb is output on pin 15 and bit 8 is output on pin 22 . bit 7 is output on pin 6 and the lsb is output on pin 13.r/ c ( pin 24 ): read / convert input . with cs low , a falling edge on r / c puts the internal sample-and-hold into the hold state and starts a conversion . with cs low , a rising edge on r/ c enables the output data bits. cs ( pin 25 ): chip select . internally or d with r / c . with r/ c low , a falling edge on cs will initiate a conversion . with r/ c high , a falling edge on cs will enable the output data . busy ( pin 26 ): output shows converter status . it is low when a conversion is in progress . data valid on the rising edge of busy . cs or r / c must be high when busy rises or another conversion will start without time for signal acquisition. v ana ( pin 27 ): 5v analog supply . bypass to ground with a 0.1f ceramic and a 10f tantalum capacitor.v dig ( pin 28 ): 5v digital supply . connect directly to pin ? 27 . functional block diagram 16-bit capacitive dac comp ref buf 2.5v ref cap (2.5v) c sample c sample ?? ? d15d0 busy control logic r/ c byte internal clock cs zeroing switches v dig v ana v in ref agnd1 agnd2 dgnd 16 1605-1/2 bd +C successive approximation register output latches 4k 4k 6k* 20k3.75k* 10kopen* *resistor values for the ltc1605-2 downloaded from: http:///
lt c1605-1/ lt c1605-2 8 160512fa for more information www.linear.com/ltc1605-1 test circuits applications information 1k 50pf 50pf dbn dbn 1k 5v 1605-1/2 tc02 a. v oh to hi-z b. v ol to hi-z load circuit for access timing load circuit for output float delay 1k c l c l dbn dbn 1k 5v 1605-1/2 tc01 a. hi-z to v oh and v ol to v oh b. hi-z to v ol and v oh to v ol autozero switch , s3 . in this acquire phase , a minimum delay of 2s will provide enough time for the sample-and- hold capacitor to acquire the analog signal . during the convert phase , s3 opens , putting the comparator into the compare mode . the input switch s2 switches c sample to ground , injecting the analog input charge onto the summing junction . this input charge is successively compared with the binary-weighted charges supplied by the capacitive dac . bit decisions are made by the high speed comparator . at the end of a conversion , the dac output balances the v in input charge . the sar contents ( a 16- bit data word ) that represents the v in are loaded into the 16- bit output latches . driving the analog inputsthe nominal input range for the ltc1605 -1 is 0v to 4v or (1.6v ref ) and for the ltc1605 -2 the input range is 4v or (1.6v ref ). the inputs are overvoltage protected to 25v. the input impedance is typically 10k; therefore , it should be driven by a low impedance source . wideband noise coupling into the input can be minimized by placing a 1000pf capacitor at the input as shown in figure 2 . an npo-type capacitor gives the lowest distortion . place the capacitor as close to the device input pin as possible . if an amplifier is to be used to drive the input , care should be taken to select an amplifier with adequate accuracy , linearity and noise for the application . the following list is a summary of the op amps that are suitable for driving the ltc1605-1/ltc1605-2. more detailed information is available in the linear technology data books and linearview tm cd-rom. conversion details the ltc1605-1/ltc1605 -2 use a successive approxima - tion algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16- bit or two byte parallel output . the adc is complete with a precision reference and an internal clock . the control logic provides easy interface to microprocessors and dsps . ( please refer to the digital interface section for the data format.) conversion start is controlled by the cs and r / c inputs . at the start of conversion , the successive approximation register ( sar ) is reset . once a conversion cycle has begun , it cannot be restarted . during the conversion , the internal 16- bit capacitive dac output is sequenced by the sar from the most significant bit ( msb ) to the least significant bit ( lsb). referring to figure 1 , v in is connected through the resistor divider and s1 to the sample-and-hold capacitor during the acquire phase and the comparator offset is nulled by the figure 1. ltc1605-1/ltc1605-2 simplified equivalent circuit v dac 1605-1/2 f01 + C c dac dac s1 sample s2 hold c sample sa r 16-bit latch comparator sample s3 r in2 r in1 v in linearview is a trademark of linear technology corporation downloaded from: http:///
lt c1605-1/ lt c1605-2 9 160512fa for more information www.linear.com/ltc1605-1 applications information lt ? 1007 - low noise precision amplifier . 2.7ma supply current 5v to 15v supplies . gain bandwidth product 8mhz. dc applications.lt1097 - low cost , low power precision amplifier . 300a supply current . 5v to 15v supplies . gain bandwidth product 0.7mhz. dc applications.lt1227 - 140mhz video current feedback amplifier . 10ma supply current . 5v to 15v supplies . low noise and low distortion.lt1360 - 37mhz voltage feedback amplifier . 3. 8ma supply current. 5v to 15v supplies. good ac/dc specs.lt1363 - 50mhz voltage feedback amplifier . 6. 3ma supply current. good ac/dc specs.lt1364/lt1365 - dual and quad 50mhz voltage feedback amplifiers. 6.3ma supply current per amplifier . good ac / dc specs.lt1468 - 90mhz, 22v/s 16-bit accurate amplifier internal voltage reference the ltc1605-1/ltc1605-2 has an on-chip, temperature compensated, curvature corrected , bandgap reference , which is factory trimmed to 2.50v. the full-scale range of the adc is equal to (1.6v ref ) or nominally 0v to 4v for the ltc1605 -1 and (1.6v ref ) or nominally 4v for the ltc1605-2. the output of the reference is connected to the input of a unity-gain buffer through a 4k resistor ( see figure 3 ). the input to the buffer or the output of the reference is available at ref ( pin 3 ). the internal refer - ence can be overdriven with an external reference if more accuracy is needed . the buffer output drives the internal dac and is available at cap ( pin 4 ). the cap pin can be used to drive a steady dc load of less than 2ma. driving an ac load is not recommended because it can cause the performance of the converter to degrade. for minimum code transition noise the ref pin and the cap pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer (2.2f tantalum). offset and gain adjustments the ltc1605-1 / ltc1605 -2 offset and full-scale er - rors have been trimmed at the factory with the external resistors shown in figure 4 . this allows for external adjustment of offset and full scale in applications where absolute accuracy is important . see figure 5 for the off - set and gain trim circuit for the ltc1605-1/ltc1605-2. first adjust the offset to zero by adjusting resistor r3. apply an input voltage of 30.5v (0.5lsb) and adjust r3 so the code is changing between 0000 0000 0000 0001 and 0000 0000 0000 0000 . the gain error is trimmed by adjusting resistor r4. an input voltage of 3.999908v (fs C 1 .5lsb) is applied to v in and r4 is adjusted until the output code is changing between 1111 1111 1111 1110 and 1111 1111 1111 1111 . figure 6a shows the unipolar transfer characteristic of the ltc1605-1.for the ltc1605-2, first adjust the offset to zero by adjusting resistor r3. apply an input voltage of C61v (C0.5lsb) and adjust r3 so the code is changing between 1111 1111 1111 1111 and 0000 0000 0000 0000 . the gain error is trimmed by adjusting resistor r4. an input voltage of 3.999817v (+fs C 1 .5lsb) is applied to v in and r4 is adjusted until the output code is changing between 0111 1111 1111 1110 and 0111 1111 1111 1111 . figure 6b shows the bipolar transfer characteristics of the ltc1605-2 . dc performanceone way of measuring the transition noise associated with a high resolution adc is to use a technique where a dc signal is applied to the input of the adc and the result - ing output codes are collected over a large number of conversions . for example , in figure 7 the distribution of output code is shown for a dc input that has been digitized 10000 times . the distribution is gaussian and the rms code transition is about 1lsb. 1605-1/2 f02 1000pf 33.2k v in cap a in 200 figure 2. analog input filtering downloaded from: http:///
lt c1605-1/ lt c1605-2 10 160512fa for more information www.linear.com/ltc1605-1 applications information input voltage (v) C fs/2 0v output code 1605-1/2 f06b 011...111 011...110000...001 000...000 111...111 111...110 100...000 100...001 C1 lsb 1 lsb bipolar zero fs/2 C 1lsb fs = 8v1lsb = fs/65536 figure 6b. ltc1605-2 bipolar transfer characteristics code 0 500 15001000 25002000 40003500 3000 4500 count 1605-1/2 f07 C5 C4 C3 C2 C1 0 1 2 3 4 5 figure 7. histogram for 10000 conversions input voltage (v) 0v output code 1605-1/2 f06a 111...111 111...110000...000 000...001 1 lsb unipolar zero fs C 1lsb fs = 4v1lsb = fs/65536 figure 6a. ltc1605-1 unipolar transfer characteristics figure 5. 0v to 4v input for the ltc1605-1 and 4v for the ltc1605-2 with offset and gain trim + 5 4 3 2 1 2.2f + 2.2f 33.2k 1% 0v to 4v or 4v input 200 1% v in agnd1ref cap agnd2 ltc1605-1ltc1605-2 1605-1/2 f05 576k r4 50k r350k offset trim gain trim 5v C + 1605-1/2 f03 internal capacitor dac bandgap reference v ana 4k 2.2f cap (2.5v) 2.2f ref (2.5v) 4 3 figure 3. internal or external reference source + 5 4 3 2 1 2.2f + 2.2f 33.2k1% 0v to 4v or 4v input 200 1% v in agnd1ref cap agnd2 ltc1605-1ltc1605-2 1605-1/2 f04 figure 4. 0v to 4v input for the ltc1605-1 and 4v for the ltc1605-2 without trim downloaded from: http:///
lt c1605-1/ lt c1605-2 11 160512fa for more information www.linear.com/ltc1605-1 applications information digital interface internal clock the adc has an internal clock that is trimmed to achieve a typical conversion time of 7s. no external adjustments are required and , with the typical acquisition time of 1s, throughput performance of 100ksps is assured. timing and control conversion start and data read are controlled by two digital inputs : cs and r / c . to start a conversion and put the sample-and-hold into the hold mode , bring cs and r/ c low for no less than 40ns. once initiated , it cannot be restarted until the conversion is complete . converter status is indicated by the busy output and this is low while the conversion is in progress. there are two modes of operation . the first mode is shown in figure 8 . the digital input r / c is used to control the start of conversion . cs is tied low . when r / c goes low , the sample-and-hold goes into the hold mode and a con - version is started . busy goes low and stays low during the conversion and will go back high after the conversion has been completed and the internal output shift registers have been updated . r / c should remain low for no less than 40ns. during the time r / c is low , the digital outputs are in a hi-z state . r / c should be brought back high within 3s after the start of the conversion to ensure that no errors occur in the digitized result . the second mode , shown in figure 9 , uses the cs signal to control the start of a con - version and the reading of the digital output . in this mode , the r / c input signal should be brought low no less than 10ns before the falling edge of cs . the minimum pulse width for cs is 40ns. when cs falls , busy goes low and will stay low until the end of the conversion . busy will go high after the conversion has been completed . the new data is valid when cs is brought back low again to initiate a read . again , it is recommended that both r / c and cs return high within 3s after the start of the conversion.output data the output data can be read as a 16- bit word or it can be read as two 8- bit bytes . the format of the output data is straight binary for the ltc1605 -1 and two s complement for the ltc1605-2. the digital input pin byte is used to control the two byte read . with the byte pin low , the first eight msbs are output on the d15 to d8 pins and the eight lsbs are output on the d7 to d0 pins . when the byte pin is taken high , the eight lsbs replace the eight msbs (figure 10). t 1 t 11 t 2 t 4 t 3 t 7 t 6 acquire convert convert acquire t 5 t 8 t acq t conv t 9 previous data valid previous data valid hi-z not valid hi-z data valid data valid r/ c busy mode data mode 1605-1/2 f08 figure 8. conversion timing with outputs enabled after conversion ( cs tied low) downloaded from: http:///
lt c1605-1/ lt c1605-2 12 160512fa for more information www.linear.com/ltc1605-1 applications information figure 9. using cs to control conversion and read timing acquire convert acquire data valid t 1 t 10 t 10 t 1 t 10 t 10 t 3 t 6 t 4 t conv t 12 t 7 hi-z hi-z r/ c busy cs mode data bus 1605-1/2 f09 figure 10. using cs and byte to control data bus read timing t 10 t 10 t 12 t 7 t 12 hi-zhi-z hi-zhi-z high byte low byte low byte high byte r/ c byte cs pins 6 to 13 pins 15 to 22 1605-1/2 f10 downloaded from: http:///
lt c1605-1/ lt c1605-2 13 160512fa for more information www.linear.com/ltc1605-1 applications information dynamic performance fft ( fast fourier transform ) test techniques are used to test the adc s frequency response , distortion and noise at the rated throughput . by applying a low distortion sine wave and analyzing the digital output using an fft algo - rithm, the adc s spectral content can be examined for frequencies outside the fundamental . figure 11 shows a typical ltc1605 -2 fft plot which yields a sinad of 87db and thd of C101.1db.signal-to-noise ratio the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other frequency components at the a / d output . the output is band limited to frequencies from above dc and below half the sampling frequency. figure 11 shows a typical sinad of 87db with a 100khz sampling rate and a 1khz input. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency . thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ... + v n 2 v1 frequency (khz) 0 magnitude (db) 1605-1/2 g07/f11 5 10 15 20 25 30 35 40 45 50 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 C130 f sample = 100khz f in = 1khz sinad = 87dbthd = 101.1db snr = 87.2db figure 11. ltc1605-2 nonaveraged 4096-point fft plot where v1 is the rms amplitude of the fundamental frequency and v2 through v n are the amplitudes of the second through nth harmonics.board layout, power supplies and decoupling wire wrap boards are not recommended for high reso - lution or high speed a / d converters . to obtain the best performance from the ltc1605-1/ltc1605-2, a printed circuit board is required . layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible . in particular , care should be taken not to run any digital track alongside an analog signal track or underneath the adc . the analog input should be screened by agnd. figures 12 through 15 show a layout for a suggested evalu - ation circuit which will help obtain the best performance from the 16- bit adc . additional information regarding the evaluation circuit and gerber files for the pc board layout are available from linear technology or your local sales office. pay particular attention to the design of the analog and digital ground planes . the dgnd pin of the ltc1605-1 / ltc1605 -2 can be tied to the analog ground plane . placing the bypass capacitor as close as possible to the power supply, the reference and reference buffer output is very important. low impedance common returns for these bypass capacitors are essential to low noise operation of the adc , and the pc track width for these lines should be as wide as possible . also , since any potential difference in grounds between the signal source and adc appears as an error voltage in series with the input signal , attention should be paid to reducing the ground circuit impedance as much as possible . the digital output latches and the onboard sampling clock have been placed on the digital ground plane . the two ground planes are tied together at the power supply ground connection. downloaded from: http:///
lt c1605-1/ lt c1605-2 14 160512fa for more information www.linear.com/ltc1605-1 applications information figure 12. component side silkscreen for the suggested ltc1605-1/ltc1605-2 evaluation circuit analog ground plane analog ground plane digital ground plane figure 13. bottom side showing analog ground plane figure 14. component side showing separate analog and digital ground plane downloaded from: http:///
lt c1605-1/ lt c1605-2 15 160512fa for more information www.linear.com/ltc1605-1 applications information d15 + 3 u6a 74hc221 ab qq cext r21, 2k rcext 15 12 413 clk 1605-1/2 f15 d15d14 u1 ltc1605-1ltc1605-2 d13d12 d11 c50.1f r1933.2k 1% c30.1f c161000pf c42.2f c22.2f ext int v ref jp1 c1710f d10 d9d8 d7 d6 d5 d4 d3 d2 d1 67 8 9 10 11 12 13 15 16 17 18 19 20 21 d0 d15 d15 d14d13 d12 d11 d10 d9 d8 23 4 5 6 7 8 9 d14d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 4 r20 1k 3 u4b 74hc04 6 5 u4c 74hc04 c115pf 22 12 3 4 5 1423 24 25 26 27 28 v in q0 u2 74hc574 19 d0 q1 18 d1 q2 17 d2 q3 16 d3 q4 15 d4 q5 14 d5 q6 13 d6 q7 1 2 12 u4a 74hc04 d7 1 oc 11 clk 27 6 5 4 3 u7 74hc160 clrload rco 15 2 3 jp3 1 ext clk int 2 3 jp5 1 v cc cs gnd enp 10 ent qd 11 d qc 12 c qb 13 b qa 14 a 2 u8 1mhz, osc out 3 gnd 1 na e2 gnd v in 7v to 15v e1 u5 lt1121 d16mbr0520 c622f 10v gnd 1 3 2 v in v in 4 u9 lt1019-2.5 trim 5 gnd 1 nc1 2 input 3 87 6 temp nc2 heater out 19 clk d0d1 d2 d3 d4 d5 d6 d7 23 4 5 6 7 8 9 q0 u3 74hc574 19 d0 q1 18 d1 q2 17 d2 q3 16 d3 q4 15 d4 q5 14 d5 q6 13 d6 q7 12 d7 1 oc 11 clk agnd1ref cap agnd2 dgnd byte r/ c csbusy v ana v dig c8 0.1f c710f v kk v cc v kk v kk v dd v cc r16 20 c90.1f c100.1f digital i.c. bypassing c110.1f c120.1f v cc c130.1f c140.1f c1510f 2 3 jp4 1 reverse byte nornal v cc v cc v cc 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 gnd gnd clk d15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 r8, 1.2k d8 r9, 1.2k d9 r10, 1.2k d10 r11, 1.2k d11 r12, 1.2k d12 r13, 1.2k d13 r14, 1.2k d14 r15, 1.2k r0, 1.2k d0 r1, 1.2k d1 r2, 1.2k d2 r3, 1.2k d3 r4, 1.2k d4 r5, 1.2k d5 r6, 1.2k d6 r7, 1.2k d7 jp2led enable 10 11 u4e 74hc04 8 1 2 9 ext_clk j1 1 2 a in j2 r17 51 u4d 74hc04 r18 200 1% figure 15. ltc1605-1 suggested evaluation circuit schematic downloaded from: http:///
lt c1605-1/ lt c1605-2 16 160512fa for more information www.linear.com/ltc1605-1 typical applications the circuit in figure 16 is an example showing the ltc1605 16- bit a / d converter and ltc1391 8-channel mux connected to a 68 hc11 controller . the ltc1605s 16- bit data output is read in two 8- bit bytes using pins 6 (msb, bi t7) through 13 (bit8, bi t0), connected to the hc11 s portc . the mux s 4- bit serial address data is sent using the controllers spi.the process to convert a channel s input signal is shown in sample listing a . it begins with shifting in the mux s channel data while the ss signal is a logic high . the mux channel address is latched on the falling edge of ss and the chosen channel s input is applied at the ltc1605s input, pin 1 . through the processor s porta , a low-going pulse is applied to the ltc1605 s r / c pin , initiating a con - version. the processor then monitors the busy output . when this signal becomes a logic high , signaling the end of conversion , the processor reads the high byte of the conversion through portc . the low byte is read through portc when the processor changes the byte signal to a logic high . the timing relationship of the control signals and data are shown in figure 17. sample listing a************************************************************************* * * * this example program selects the an ltc1391 mux channel, initiates a * * conversion, and retrieves conversion data. it stores the 16-bit data * * in two consecutive memory locations. the program is designed for use * * with the ltc1605s /cs tied to ground (see timing diagram in * * figure 17). * * * ************************************************************************** ***************************************** * 68hc11 register deinitions * ***************************************** * porta equ $1000 parallel port a * use bit0 as an input for the ltc1605s /busy signal * use bit3 as an output driving the ltc1605s byte * input pioc equ $1002 parallel i/o control register * staf,stai,cwom,hnds, oin, pls, ega,invb portc equ $1003 port c data register * bit7,bit6,bit5,bit4,bit3,bit2,bit1,bit0 ddrc equ $1007 port d data direction register * bit7,bit6,bit5,bit4,bit3,bit2,bit1,bit0 * 1 = output, 0 = input portd equ $1008 port d data register * - , - , ss* ,csk ;mosi,miso,txd ,rxd ddrd equ $1009 port d data direction register spcr equ $1028 spi control register * spie,spe ,dwom,mstr;spol,cpha,spr1,spr0 spsr equ $1029 spi status register * spif,wcol, - ,modf; - , - , - , - spdr equ $102a spi data register; read-bufer; write-shifter ** ram variables to hold the ltc1605s 14 conversion result * din1 equ $00 this memory location holds the ltc1605s bits 15 - 08 din2 equ $01 this memory location holds the ltc1605s bits 07 - 00 mux equ $02 this memory location holds the mux address data * downloaded from: http:///
lt c1605-1/ lt c1605-2 17 160512fa for more information www.linear.com/ltc1605-1 typical applications ***************************************** * start getdata routine * ***************************************** * org $c000 program start location init1 ldaa #$03 0,0,0,0,0,0,1,1 * staf=0,stai=0,cwom=0,hnds=0, oin=0, pls=0, ega=1,invb=1 staa pioc ensures that the pioc registers status is the same * as after a reset, necessary of simple port d manipulation ldaa #$00 0,0,0,0,0,0,0,0 * bits 7 - 0 are used as inputs for the ltc1605s data staa ddrc direction of portds bit are now set as inputs ldaa #$2f -,-,1,0;1,1,1,1 * -, -, ss*-hi, sck-lo, mosi-hi, miso-hi, x, x staa portd keeps ss* a logic high when ddrd, bit5 is set ldaa #$38 -,-,1,1;1,0,0,0 staa ddrd ss* , sck, mosi are conigured as outputs * miso, txd, rxd are conigured as inputs * ddrds bit5 is a 1 so that port ds ss* pin is a general output ldaa #$50 staa spcr the spi is conigured as master, cpha = 0, cpol = 0 * and the clock rate is e/2 * (this assumes an e-clock frequency of 4mhz. for higher * e-clock frequencies, change the above value of $50 to a * value that ensures the sck frequency is 2mhz or less.) getdata pshx pshy psha * ***************************************** * setup indices * ***************************************** * ldx #$0 the x register is used as a pointer to the memory * locations that hold the conversion data ldy #$1000 * ***************************************** * ensure that a logic high is applied * * to the ltc1391s /cs and the * * ltc1605s r/c pins * ***************************************** * bset portd,y %00100000 this sets the ss* output bit to a logic * high, ensuring that the ltc1391s cs* * input is a logic high while clocking * mux address data into the ltc1391 bset porta,y %00010000 this sets the r/c* output bit to a logic * high, ensuring that the ltc1605s r/c* * input is a logic high before initiating * a conversion ***************************************** downloaded from: http:///
lt c1605-1/ lt c1605-2 18 160512fa for more information www.linear.com/ltc1605-1 typical applications * retrieve the mux address from memory * * and send it to the ltc1391 * ***************************************** * ldaa mux retrieve the mux address from memory oraa #$08 enable the selected mux address staa spdr select the mux channel wait1 ldaa spsr this loop waits for the spi to complete a serial * transfer/exchange by reading the spi status register bpl wait1 the spif (spi transfer complete lag) bit is the spsrs * msb and is set to one at the end of an spi transfer. the * branch will occur while spif is a zero. bclr portd,y %00100000 this forces a logic low on portds ss*, * latching the muxes data ****************************************** * initiate a ltc1605 conversion * ***************************************** * bclr porta,y %00010000 initiate a conversion bset porta,y %00010000 this sets the ltc1605s r/c* to a logic * high * ***************************************** * set the ltc1605s byte input low to * * ensure that the high byte is present * * during the irst read * ***************************************** * ldaa porta get the contents of port a anda #%11110111 set bit3 low staa porta set the ltc1605s byte input low ****************************************** * the next short loop ensures that the * * ltc1605s conversion is inished * * before starting the data transfer * ***************************************** * convend ldaa porta retrieve the contents of port a anda #%00000001 look at bit0 * bit0 = lo; the ltc1605s conversion is not * complete * bit0 = hi; the ltc1605s conversion is complete beq convend branch to the loops beginning while bit7 * remains low * downloaded from: http:///
lt c1605-1/ lt c1605-2 19 160512fa for more information www.linear.com/ltc1605-1 typical applications ************************************************************************* * this routine retrieves the ltc1605s 16-bit data using two 8-bit * * reads. the byte input is manipulated through port as bit3. during * * the irst read when byte is low, the upper byte is read and stored in * * din1. during the second read when byte is high, the lower byte is * * read and stored in din2. * ************************************************************************* * ldaa portc retrieve the ltc1605s high byte staa din1 store the high byte ldaa porta get the contents of port a oraa #%00001000 set bit3 high staa porta set the ltc1605s byte input high ldaa portc retrieve the ltc1605s low byte staa din2 store the high byte pula restore the a register puly restore the y register pulx restore the x register rts figure 16. 8-channel, 16-bit data acquisition system with interface to the 68hc11 v dig v ana ltc1605-1ltc1605-2 d7/d15d6/d14 d5/d13 d4/d12 d3/d11 d2/d10 d1/d9d0/d8 2827 6 7 8 9 10 11 12 13 18 v + d ltc1391 v C d out d in cs dlk dgnd 16 1514 5v 0.1f 1312 11 10 9 m0s1 ss spi clk 12 3 4 5 6 7 8 s0s1 s2 s3 s4 s5 s6 s7 1716 15 26 25 r/ c 24 byte 23 portc, bit7portc, bit6 portc, bit5 portc, bit4 portc, bit3 portc, bit2 portc, bit1 portc, bit0 porta, bit0 porta, bit4 porta, bit3 2019 14 1605-1/2 f16 14 5 3 2221 v in capagnd2 dgnd ref 2 agnd1 busy cs 2.2f 0.1f 0.1f 5v 5v 8 1 32 4 2.2f 33.2k 1% 200 1% 10f 1f 5v + + C + use for ltc1605-2 1/2 lt1630 C5v supply forltc1605-2 downloaded from: http:///
lt c1605-1/ lt c1605-2 20 160512fa for more information www.linear.com/ltc1605-1 package description g package 28-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) dimensions in inches (millimeters) unless otherwise noted. g28 ssop 1098 0.13 C 0.22 (0.005 C 0.009) 0? ? 8? 0.55 ? 0.95 (0.022 ? 0.037) 5.20 ? 5.38** (0.205 ? 0.212) 7.65 ? 7.90 (0.301 ? 0.311) 1 2 3 4 5 6 7 8 9 10 11 12 1413 10.07 ? 10.33* (0.397 ? 0.407) 2526 22 21 20 19 18 17 16 15 2324 2728 1.73 ? 1.99 (0.068 ? 0.078) 0.05 ? 0.21 (0.002 ? 0.008) 0.65 (0.0256) bsc 0.25 ? 0.38 (0.010 ? 0.015) note: dimensions are in millimetersdimensions do not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side dimensions do not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side * ** n package 28-lead pdip (narrow 0.300) (reference ltc dwg # 05-08-1510 rev i) obsolete package downloaded from: http:/// n28 rev i 0711 1.400* (35.560) max 3 4 5 6 7 8 9 10 11 12 21 13 14 15 16 18 17 19 20 22 23 24 25 26 2 27 1 28 .020 (0.508) min .120 (3.048) min .130 t .005 (3.302 t 0.127) .065 (1.651) typ .045 ? .065 (1.143 ? 1.651) .018 t .003 (0.457 t 0.076) .005 (0.127) min .008 ? .015 (0.203 ? 0.381) .300 ? .325 (7.620 ? 8.255) .325 +.035?.015 +0.889?0.381 8.255 note:1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc .240 ? .295* (6.096 ? 7.493) n package 28-lead plastic pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510 rev i)
lt c1605-1/ lt c1605-2 21 160512fa for more information www.linear.com/ltc1605-1 information furnished by linear technology c orporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 07/15 obsoleted 28-lead pdip package 2, 20 downloaded from: http:///
lt c1605-1/ lt c1605-2 22 160512fa for more information www.linear.com/ltc1605-1 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 ? linear technology corporation 1999 lt 0715 rev a ? printed in the usa (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc1605-1 related parts typical application part number description comments lt ? 1019-2.5 precision bandgap reference 0.05% max, 5ppm/c max ltc1274/ltc1277 low power 12-bit, 100ksps adcs 10mw power dissipation, parallel/byte interface ltc1415 single 5v, 12-bit, 1.25msps adc 55mw power dissipation, 72db sinad ltc1419 low power 14-bit, 800ksps adc true 14-bit linearity, 81.5db sinad, 150mw dissipation lt1460-2.5 micropower precision series reference 0.075% max, 10ppm/c max, only 130a supply current ltc1594/ltc1598 micropower 4-/8-channel 12-bit adcs serial i/o, 3v and 5v versions ltc1604 16-bit, 333ksps sampling adc 2.5v input, 90db sinad, 100db thd ltc1605 low power 100ksps 16-bit adc single 5v, 10v inputs r/ c busy byte adc data mux cs mux data hi byte lo byte data 0 data 1 hi byte lo byte hi byte lo byte ch0 ch1 ch2 1605-1/2 f17 figure 17. this is the timing relationship between the selected mux channel, its conversion data and the adc and mux control signals when using the sample program in listing 1. the conversion process is latency free: the data is always generated based on the currently selected mux input downloaded from: http:///

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